In the last few years, there has been an increased interest in the electronic industry for trench storage devices commonly used in high density and high speed memory cell devices, such as dynamic random access memory devices (DRAMs) and microprocessors. Research and development efforts are made on an ongoing basis to develop faster and, correspondingly, smaller devices.
DRAMs typically include a switching transistor coupled to a storage capacitor structure. Of late, trench storage have become commonplace in DRAM products due to the high degree of planarity obtainable during wafer manufacturing associated with the trench structure.
One of the challenges associated with trench DRAM processing is the formation of an electrical connection between the trench capacitor and the diffusion region of the array device pass transistor.
A trench DRAM which has been used successfully is a small size device which features a self-aligned (also referred to as a borderless) bitline contact, referred to as a BuriED STrap device (BEST). This DRAM is described in an article by Nesbit et al. entitled "A 0.6 .mu.m.sup.2 256Mb Trench DRAM", published in the 1993 IEDM Technical Digest, pp. 627-630. This BEST cell is based on the Merged Isolation and Node Trench (MINT) cell described by Kenney et al. in an article entitled: "A buried-plate trench cell for a 64-Mb DRAM", published in the 1992 Symposium on VLSI Technology Digest of Technical Papers, pp. 14-15. BEST cells are described as having the unique feature of a self-aligned buried strap which is formed at the intersection of the storage trench and the array device. The array device channel region is gated by a field-effect transistor which must be separated from the outdiffused region of the buried strap. Thus, a buried strap connection is made between the top of the trench and the diffusion. The advantage of a buried strap connection resides in the elimination of a distinct lithographic patterning level which allows lowering the cost associated with the manufacturing of the device and improves its overall reliability.
By way of example, a prior art MINT-BEST cell with a self-aligned buried strap is shown in FIG. 1. The N junction diffusion and strap outdiffusion regions are merged forming an electrical connection between the active array device transistor (polysilicon wordline gate conductor "poly WL") at the left side of the figure, and the deep trench capacitor. An inactive (or "passing") wordline gate conductor at the right of FIG. 1 passes over the storage trench and is electrically isolated from the strap and trench regions by an extension of the shallow trench isolation (STI) dielectric.
Deep trenches are conventionally formed into substrate 50 and thin-film 100 (e.g., Si.sub.3 N.sub.4) using photolithography and reactive ion etch (RIE), with feed gases such as NF.sub.3, HBr, O.sub.2, N.sub.2, Cl.sub.2 and HCl. The surfaces are cleaned with a wet solution typically containing HF. Next, a thin node capacitor dielectric 200 is formed on the trench surfaces. An example is low pressure chemical vapor deposition (LPCVD) nitride deposited with source gases NH.sub.3 and dichlorosilane. Next, the trench is filled with a conductor to form one plate of the capacitor. In the structure shown in FIG. 1, LPCVD n+ doped polysilicon fill #1 300 is used to form this plate. A dry etch using feed gases such as SF.sub.6 planarizes the polysilicon and recesses it down inside the trench. The thin capacitor node dielectric is stripped from the upper portion of the trench which is no longer filled with polysilicon. The collar oxide 400 is then formed using a thermal oxidation in an oxidation containing ambient at 900.degree. C.-1100.degree. C. A dielectric forming the trench collar is deposited, preferably using LPCVD. An anisotropic etch of the collar dielectric creates a collar spacer 400. The etch can be RIE using feed gases such as CHF.sub.3, CF.sub.4, C.sub.4 F.sub.8, C.sub.3 FH.sub.8, C.sub.2 F.sub.6, N.sub.2, O.sub.2, and or CO. These steps are not described with drawings since they are know to those skilled in the art of trench capacitor formation.
Practitioners of the art will readily recognize that the collar may also be formed by alternative means, although this is not the subject of this invention.
The MINT-BEST cell described in the aforementioned article suffers from various drawbacks:
1) The presence of the buried strap outdiffusion and variations of the trench placement relative to the gate conductor (GC) of the active array device interferes with the electrical properties of the transistor such as the threshold voltage and the off-current.
2) Variations in the position of the passive wordline on top of the trench can block the ion implantation used to form the array transistor junction which is closest to the trench, and
3) The array cell area compaction is limited by the need to maintain a physical separation between the strap outdiffusion region and the active device channel region.
Other related references that describe depletion of majority carrier devices may be found in U.S. Pat. No. 4,907,407 issued on Mar. 9, 1990 to Kato et al., wherein the depletion transistor is provided on a thick insulator layer having its source and drain regions separated from each other by a channel region and a thin dielectric film formed on the channel region. The transistor device is connected to a storage capacitor typical of DRAM cells.
U.S. Pat. No. 5,198,995 issued to Dennard on Mar. 30, 1993, and of common assignee, describes a substrate-plate trench capacitor type cell structure having a lightly depleted PMOS access device with p+polysilicon gate. Such a device is described having the advantage of providing the DRAM cell with a reduced electric field or a higher stored charge for a given electric field.
As DRAMs increase in storage capacity, it is desired to decrease the amount of chip area required for storing each bit of data. The area of the array needs to be scaled appropriately to adjust the DRAM bit count per chip. A potential scale limitation associated with the trench DRAM array cell structure is introduced by the area required by the pass transistor. Therefore, it is advantageous to place the array transistor directly over the trench or in close proximity to the trench storage capacitor to decrease the area 10 of the array cell.
Various configurations placing the array transistors near the trench storage capacitor have been advanced, e.g., in U.S. Pat. Nos. 5,555,206; 5,148,393; and 3,986,180, wherein the depletion mode device in the DRAM cell is placed in series with the storage capacitor. Alternatively, a configuration described in U.S. Pat. No. 5,321,285, a depletion region adjacent to the source/drain region of the transistor is used as a storage cell in a memory array.
However, the above described structures suffer from a drawback in that the transistor and capacitor regions occupy adjacent regions of the layout and do not overlap. Hence, examples of the prior art cannot be compacted to accommodate cell scaling and further miniaturization. Additionally, the above-described structures rely on the formation of an inversion layer to modulate conduction in the channel region.